Digital comparator circuits (comparators) are required in various digital control, computer, and logic applications. A typical application of comparators is the decoding or recognition of a data word. It is highly desirable that comparators (as well as the other components in the digital circuit) be capable of high speed operation.
One problem with most prior art comparators of the type illustrated in FIG. 1 (more fully described below in the Detailed Description) is that they are often formed from an extended logic gate configuration arranged in series. Consequently, they require a relatively long time to process each digital word. When the number of digital words that are being compared in most digital computers are considered, it becomes evident that the use of relatively slow digital comparator devices adds considerable time to digital processing, computing, and storing.
In U.S. Pat. No. 5,031,147, titled "Semiconductor Memory", issued Jul. 9, 1991 to Maruyama et al., a counter comparator is disclosed having exclusive OR (hereafter referred to as "XOR") circuits followed by a static NOR, a clocked inverter, and a latch. The clocked inverter provides isolation between the latch and the NOR while the XOR outputs are changing. For wide comparator circuits which compare relatively long data words, the static NOR will require a relatively long time to process a compare command.
It would accordingly be desirable to form a comparator circuit which could operate reliably with fewer stages, and thereby provide a faster comparator circuit. It would be highly desirable that such a comparator circuit accomplish this operation with fewer components arranged in series.